1. Field of the Invention
The present invention relates to a system for verifying semiconductor integrated circuits, more particularly, to a verification system that includes simulation of semiconductor integrated circuits.
2. Description of Related Art
The work of creating test patterns for testing large-scale and complex LSI circuits makes up a large portion of the time required for designing LSI devices. Sometimes test patterns created for design function verification are selected in a combination that yields high fault coverage and used for manufacturing testing, but the problem with this approach is that the quality of the selected test patterns often does not yield a fault coverage that is believed to be sufficient for the manufacturing test. Test patterns for function verification are created based on the criterion that each function within the design is being executed correctly, but this is different than the criterion that faults in the circuitry are detected. In the case of large-scale circuits, since a tremendous amount of time would be required to execute fault simulations in order to find the fault coverage, test patterns are selected by conducting fault simulations that involve sampling faults and by selecting based on the activation rates of signals found in logic simulations. These methods do not enable the fault coverage to be found accurately.
Design for testability (DFT) is a technology in which test circuits that are as small-scale as possible are added to an LSI circuit in order to increase the ease with which the LSI circuit can be tested and optimize the test pattern creation time, test pattern size, testing time, and final fault coverage. Representative examples of DFT technologies include scan design, memory BIST, and logic BIST.
Scan design is a DFT technology that has been used widely in this area. As shown in FIG. 9, all of the registers 334 (flip flops or latches) inside a sequential circuit are converted to special registers called scan registers and connected serially as at least one shift register (scan path). Use of this structure enables the normally difficult task of controlling and observing the internal registers of the circuit to be accomplished directly by using external input and output terminals. As a result, the work of creating test patterns is greatly simplified. In particular, by using a program to conduct automatic test pattern generation (ATPG), test patterns having high fault coverage can be created in a short amount of time.
There are several design rules which must be obeyed when using ATPG to automatically generate test patterns for a scan-designed circuit. If portions that are not in accordance with these rules remain in the circuit, the possibility will exist that the generated test patterns are not correct. Additionally, in many cases, the ATPG tool handles the circuit as a completely synchronized circuit and generates the patterns based on the assumption that the clock is applied to all registers simultaneously. Consequently, it is feasible that the actual circuit will not operate correctly in cases where clock skewing has occurred. Because of these issues, it is sometimes necessary to simulate the generated test patterns and verify that they are correct.
The scan test patterns are made up chiefly of shift cycles during which test data is sent to and received from the scan path and cycles during which the logic circuit executes system operations. The latter are made up of external input settings, system clock input, and external output monitoring and can be executed with one cycle. The logic simulation, of course, involves simulating all of these operations.
The problem is the time required for the shift cycle. During shift operations, the output of the scan register changes randomly and the resulting events propagate to the inside of the logic circuit. In many cases it is not actually necessary to simulate these operations. For example, in the case of a full scan circuit, it is the signal value set in the register at the point in time when the shift is completed that is important and, thus, operations taking place during the shift are totally unrelated to the test. However, it is actually this shift operation portion that requires the most time for simulation.
A technique called parallel load simulation is used to curtail this kind of unnecessary simulation time. In parallel load simulation, instead of simulating the shift cycle, the scan in pattern is assigned directly to the register and the register values are observed directly. There are various methods of direct assignment, including assigning the scan in pattern to the output signal of the register and assigning the scan in pattern to the scan input and applying the scan clock once only.
FIG. 10 is an example circuit for explaining the parallel load simulation technique. This simulation is as follows. (1) A test pattern is assigned directly to a register 342 connected to a combinational circuit 341. (2) An input pattern is fed to an external input 343. (3) An external output 344 is checked after a prescribed amount of time and, then, a system clock is applied to the register in a normal mode and the test results are captured. (4) The values of the register 342 are observed directly and compared with expected values. These operations are all executed with respect to all patterns. If necessary, the test mode is selected when setting and observing values of the register.
The parallel load simulation technology greatly reduces the verification simulation time of the scan test patterns. However, there are still problems in comparison with a simple simulation, e.g., the fact that the shift operation portion is not simulated and necessity to create test patterns for PLS from scan test patterns.
One widely used testability technique for resolving the difficulty of testing large-scale, complex semiconductor integrated circuits is BIST (built-in self test). BIST involves both generating test patterns to be applied to blocks targeted for testing and analyzing the test result output from the blocks targeted for testing in a fully automatic fashion using a logic circuit provided in the periphery of the targeted test blocks.
FIG. 11 shows a general configuration for BIST. The external input signal 352 for the test mode setting is used to set the semiconductor integrated circuit, including a block 356 targeted for testing, to test mode. In test mode, the input and output of the block targeted for testing are connected to input and output signals for testing that are different than during normal operation. After the BIST circuit is initialized, the self test is executed by setting the BIST clock 353 in a pre-defined times. The test mode signal and the BIST clock are fed directly from an external input signal or through a BIST control circuit 351. While the self test is being executed, the input 355 to the block 356 targeted for testing is generated automatically by a test pattern generator 354 and the test patterns are fed to the block 356 targeted for testing through the test pattern output 355. The test result output 357 from the block targeted for testing is fed to a test result analyzer 358 where it is compared with expected values in a consecutive fashion or converted into compressed data (signature) of a prescribed bit length. Finally, the test analysis results 359 for the block 356 targeted for testing are outputted and a determination is made as to whether the test results are good or bad.
With BIST, it is not necessary to prepare test patterns stored in an external test memory and the cost of the tester is curtailed. Since all operations are executed within the device in synchronization with the BIST clock, it is possible to conduct tests at a higher operating speed than the test operating frequency of the tester by setting the BIST clock so as to achieve a high operating speed. Consequently, product testing can be conducted at a speed that is close to actual operation. Since a small number of external input and output signals for testing are all that is required to perform BIST, a plurality of blocks can be tested in a parallel manner. This can greatly curtail the total test time.
Depending on the type of block targeting for testing, BIST can be divided into memory BIST performed with respect to memory devices and logic BIST performed with respect to logic blocks. With respect to memory devices, the input pattern generator generates algorithm-like regular patterns because of the structure and operational regularity of memory devices. Conversely, with respect to logic blocks, a pseudo-random pattern generator (PRPG) is used because the operation of logic blocks is generally random. A linear feedback shift register (LFSR) is often used as the random pattern generator because of the simplicity of its structure.
BIST technology is currently used widely with respect to memory. The BIST circuit sequentially and automatically generates data input, address input, and a control signal for making the memory perform read and write operations and feeds these signals to the memory inputs. Analysis as to whether or not the memory output is correct when the memory performs the read operation is executed within the BIST circuit. Examples of the method of analysis include the comparator method, whereby the readout data are compared to expected values generated sequentially inside the BIST circuit, and the compressor method, whereby the data are sequentially compressed and the final compression results are compared to pre-calculated expected values.
FIG. 12 illustrates the configuration of a general memory BIST circuit. The BIST control circuit 362 inside the BIST circuit 361 sequentially generates signals required for controlling the data generator 363, the address generator 364, and the control signal generator 365. The generated signals are fed to the inputs of the memory 366. The memory output is fed to the result analyzer 367 and a determination as to whether the memory is good or bad is provided as a test result determination signal 368.
The testing executed by the BIST circuit is performed in the following order: initialization of BIST circuit, execution of BIST, determination of BIST results. Since the test is advance by merely applying a clock signal from the outside, BIST can be conducted without executing complex control operations. This feature gives BIST circuits the advantage of being easy to use in parallel testing conducted in parallel with another test circuit.
When a memory BIST circuit is inserted in the design, a simulation is conducted for verification of the BIST circuit. The simulation execution time depends on the size of the memory and often becomes very long in the case of large-scale memories, such as DRAMs. In the case of memory BIST, it is chiefly the BIST circuit, the memory targeted for BIST, and the peripheral circuitry controlling the testing that require verification. If the clock input for the BIST or the memory is propagating to other user logic circuits, that circuit portion will operate during execution of the BIST test and cause extra simulation time to be required. In the case of large-scale LSI, in which the logic portion is large, the increase in simulation is sometimes quite significant. One method of avoiding this situation is to add a circuit that suppresses propagation of the clock signal to other logics during execution of the BIST, but this involves adding a circuit that is not actually necessary and presents the possibility of making the clock design more complex. Another method is to create netlist for a BIST simulation from which the logic portions that do not require simulation have been deleted. With this method, although simulation of unnecessary circuit portions is avoided, a separate netlist must be created for simulation. Furthermore, when simulation with delay is performed, errors sometimes occur when the system attempts to assign delays to the circuit portions that have been deleted from the delay information file, resulting in a large amount of message output.
There are several methods of logic BIST but the most popular in recent years is Self-Testing Using MISR and Parallel SRSGs (STUMPS). SRSG stands for Shift Register Sequence Generator and is synonymous with the previously mentioned PRPG (Pseudo-Random Pattern Generator). STUMPS is one of the logic BIST techniques called “serial BIST.” In serial BIST, the application of the test patterns from the pattern generator and the capturing of the test results inside the pattern compressor are conducted using serial access. One of the advantages of serial BIST is that the scan design inside the logic circuit can be used as is. In other words, if the circuit is already scan designed, the increase in circuit size caused by BIST will be comparatively small and there will be no additional degradation in performance.
FIG. 13 is a schematic view of the STUMPS structure. A portion or all of the registers inside the logic circuit 371 targeted for testing are replaced by scan registers and are made up of scan paths 373. The input and output of the logic circuit 371 targeted for testing must be controlled and observed during the testing and this is accomplished by inserting scan registers and composing shift registers. The shift registers are normally configured to share a boundary scan circuit that is in compliance with IEEE 1149.1. The logic BIST circuit is made up of a pattern generator 374, a test result compressor 375, etc. The control of all of the test circuits and the supply of the scan shift clock are conducted through a logic BIST control circuit 379.
A test conducted using the STUMPS structure shown in FIG. 13 is conducted according to the following procedure. First, initial values that will serve as seed values for generating pseudo-random numbers are set into the pattern generator. It is acceptable that the initial values are not-all “0” values that has at least one “1” bit in the values. The test pattern generator 374 begins generating pseudo-random patterns at the next clock cycle. The generated patterns are fed sequentially to the scan paths 373 inside the logic circuit 371 targeted for testing. Once a pattern has been set into all of the scan paths 373 inside the logic circuit 371 targeted for testing, the value of the controllable input (external input and scan register) of the logic circuit 371 targeted for testing is thereby determined. At this point, the system clock is inputted once and values are captured in a register on the output side. Next, the scan paths 373 inside the logic circuit 371 targeted for testing are shifted and the test results are compressed while sequentially capturing the values in the test result compressor 375. This completes one application of a test pattern to the logic circuit 371 targeted for testing. This operation is repeated for each test pattern and the final value in the compressor is used as a signature and compared to the expected value to determine if the circuit is good or bad. The shift of the test result to the compressor and the input of the next pattern normally occur simultaneously. The number of scan paths is arbitrary but the larger the number of scan paths is, the shorter the shift time is and the more the time required for applying the test patterns can be reduced. Since the time required for shifting in a pattern depends on the length of the longest scan path, the use of a large number of scan paths is more effective if the path lengths are uniform.
After a logic BIST circuit has been mounted inside the design, it is necessary to conduct a simulation for verification. Since full scan design is standard for STUMPS circuits, it is futile to conduct a simulation related to the operation of the logic circuit portion during scan shifting as is done in the case of scan design. If a parallel load simulation is conducted with respect to a logic BIST circuit in the same manner as in the case of scan design, the following problems will occur. Firstly, since the input patterns to be scan shifted are generated automatically by the pseudo-random pattern generator inside the LSI, the input patterns cannot be known based on the patterns applied from the outside. Additionally, although the patterns to be shifted out are obtained when the shift clock is applied and the output of the combinational circuit portion is captured in the scan register, in the case of STUMPS these patterns are inputted to the compressor and only the compressed result can be known based on the patterns applied from the outside.
The following procedure is required to conduct parallel load simulation under these conditions. (1) Calculate the patterns to be assigned to the scan paths based on the structure of the pseudo-random pattern generator. (2) Assign the patterns directly to the scan register and, after the clock input, monitor the output of the scan register directly. (3) Calculate the compression results for the case of shift output based on the observed register output. (4) Compare the final compression result to the expected compression value outputted from the tool. The only portion of this procedure that is the same as parallel load simulation for scan design is step (2). The problems are that additional processing is required in comparison with simple simulation described previously and that the pattern generator, compressor, and scan shift portions are not simulated. Regarding the latter problem, the operation of said portions must be verified using a separate method.